module fsm(/*AUTOARG*/
   // Outputs
   o_state,
   // Inputs
   clk, reset, start
   );
   output logic [2:0] o_state;
   input logic 	      clk, reset;
   input logic 	      start;
   

   logic StateIdle, StateA, StateB;
   logic StartIdle, StartA, StartB;
   
   assign StartIdle = StateB;
   assign StartA = StateIdle & start;
   assign StartB = StateA;

   assign o_state = {StateB, StateA, StateIdle};
   

   always_ff@(posedge clk)
     begin
	if(reset)
	  begin
	     StateIdle <= 1'b1;	// ??
	     StateA <= 1'b0;
	     StateB <= 1'b0;
	  end
	else
	  begin
	     if(StartA)
	       StateIdle <= 1'b0;
	     else if(StartIdle)
	       StateIdle <= 1'b1;
	     
	     if(StartB)
	       StateA <= 1'b0;
	     else if(StartA)
	       StateA <= 1'b1;
	     
	     if(StartIdle)
	       StateB <= 1'b0;
	     else if(StartB)
	       StateB <= 1'b1;

	  end
     end // always_ff@

endmodule

module tb();
   logic [2:0] state;
   logic       clk = 1'b0;
   logic       reset;
   logic       start;
   
   fsm U_fsm(
	     // Outputs
	     .o_state			(state),
	     // Inputs
	     .clk			(clk),
	     .reset			(reset),
	     .start			(start));


   always #5 clk = ~clk;
   initial begin
      reset = 1'b1;
      start = 1'b0;
      #10 reset = 1'b0;
      
      #100 start = 1'b1;
      #10 start = 1'b0;
      
      
   end
   
endmodule // tb
